Conventional approaches to implementing digital logic on an integrated circuit provide an input pin that detects either a HIGH (e.g., a "1") or a LOW (e.g., a "0") state. A number of such pins are implemented to perform various operations, such as I/O or addressing.
It may be desirable to use a pin dedicated to trigger a specific event in the integrated circuit. One such event would be to enter a test mode where such a dedicated input pin is used to trigger the test mode. With such an arrangement, the dedicated pin generally does not perform other functions, such as I/O or addressing. Since it is generally desirable to reduce the overall number of pins on an integrated circuit, this solution may not be desirable in certain design applications, such as high pin count devices.